3 Common STM32 Timer Mistakes That Give You the Wrong PWM Frequency

The symptom: PSC and ARR look right, but the frequency is wrong

STM32 timer math is compact enough to fit in one line, yet small assumptions can move a PWM output far from its target. Before changing firmware at random, check the timer clock, the register offsets, and the way you chose PSC and ARR. The examples below use an up-counting, edge-aligned time base.

Mistake #1: forgetting both “+1” terms

For this mode, the project calculator uses:

counterClock = timerClock / (PSC + 1)
PWM frequency = timerClock / ((PSC + 1) × (ARR + 1))
period = 1 / PWM frequency
duty = CCR / (ARR + 1) × 100%

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The register values are zero-based. PSC=71 means a divide-by-72 prescaler, not divide-by-71. Likewise, an up-counter that runs from 0 through ARR=999 has 1,000 timer ticks per period. Using timerClock / (PSC × ARR) introduces two independent off-by-one errors and is especially misleading when either register is zero.

Mistake #2: using the wrong timer input clock

The CPU frequency is not automatically the input clock of every timer. Start at the clock tree: identify the APB bus, its prescaler, and the effective clock routed to the specific timer instance. Some STM32 families apply a timer-clock multiplication rule when an APB prescaler is not 1; other families and timer domains have different details. Treat that as a device-specific rule, not a universal STM32 constant.

The calculator’s timerClock field means this effective input clock in hertz. If you enter the APB peripheral clock when the timer receives another value, the arithmetic can be internally correct and still disagree with the pin waveform. The exact reference manual for the MCU and its clock configuration is the authority.

Mistake #3: guessing PSC and ARR

PSC and ARR are a pair. Many integer pairs can produce the same frequency, but they do not provide the same counter rate or duty-cycle resolution.

• PSC sets the counter clock after prescaling.
• ARR sets the number of counter ticks in a period.
• CCR sets the compare point. With PWM mode 1, edge alignment and active-high polarity, CCR / (ARR + 1) is the ideal duty calculation.
• Both PSC and ARR must fit the selected timer width, and CCR must be within the useful range for ARR.

Choosing a pair is therefore a design decision, not a guessing game. A larger ARR generally gives more discrete compare values for duty control. The target-frequency solver in the calculator searches valid integer pairs, minimizes relative frequency error, and reports that error; it is still your responsibility to check the timer’s actual capabilities and clock setup.

Worked example: 72 MHz timer clock, 1 kHz PWM

Suppose the clock tree and reference manual establish a 72,000,000 Hz timer input. Use PSC=71, ARR=999, and CCR=250.

1. Counter clock = 72,000,000 / (71 + 1) = 1,000,000 Hz.
2. Period ticks = 999 + 1 = 1,000.
3. PWM frequency = 1,000,000 / 1,000 = 1,000 Hz; period = 1 ms.
4. Ideal duty = 250 / 1,000 × 100 = 25%.

The same formula gives useful cross-checks:

Timer clock PSC ARR CCR Counter clock PWM frequency Duty 72 MHz 71 999 250 1 MHz 1 kHz 25% 72 MHz 719 999 500 100 kHz 100 Hz 50% 80 MHz 79 999 750 1 MHz 1 kHz 75%

These are arithmetic examples, not measurements. Startup timing, preload and update events, oscillator tolerance, output polarity, interrupts, DMA and board effects can change what an instrument observes.

Verify instead of guessing

I develop and maintain the STM32 Timer & PWM Calculator. It calculates counter clock, period, PWM frequency and ideal edge-aligned duty from timer clock, width, PSC, ARR and CCR, and includes a target-frequency solver with an error value.

To reproduce the worked example, enter 72000000 Hz, choose 16-bit, enter PSC 71, ARR 999, and CCR 250, then select Calculate. Check for 1 MHz counter clock, 1 kHz PWM frequency, 1 ms period and 25% duty. This is a repeatable arithmetic check, not an official STM32 configuration wizard or a hardware verification report.

A short debugging checklist

• Check the effective timer input clock in the MCU clock tree.
• Keep both PSC + 1 and ARR + 1 terms.
• Confirm the timer width and register ranges.
• Decide whether your chosen ARR provides enough duty resolution.
• Check CCR against ARR and the selected PWM polarity/mode.
• Compare the calculated result with the exact device reference manual.
• Measure the final waveform separately when hardware behavior matters.

References and disclosure

ST’s AN4776 timer cookbook gives official timer and PWM configuration examples. STM32F1 users can also consult the timer and RCC chapters of RM0008. Other STM32 families require their matching manuals.

AI assisted with drafting and language editing. The equations and numerical examples were independently recomputed from the stated model. No hardware measurements, user testimonials or performance guarantees are claimed.