True story from an AXI interconnect project.
We had a well-verified slave. 500k+ simulation cycles. Code coverage > 98%. The DV team signed off. Tapeout was 2 weeks away.
Then a senior architect asked a simple question: “What happens if AWLEN wraps around 256 when AWBURST is INCR?”
The spec said it was “undefined behavior.” Our testbench skipped undefined sequences. The RTL had a latent state machine hang hiding in that corner.
We caught it. Others don’t.
What I learned: Verification is not about proving the RTL matches the spec. It’s about proving the spec is correct before the RTL implements it. These are two completely different problems.
The bugs that cause respins aren’t usually in the code. They’re in the assumptions nobody thought to question.
If you’re a verification engineer reading this — your most valuable skill isn’t knowing UVM. It’s knowing which questions to ask that your spec author forgot to answer.
Hashtags: #HardwareVerification #ASIC #AXI #ChipDesign #Tapeout #SystemVerilog #SiliconEngineering
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